Building a RAM Board

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glitch
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Building a RAM Board

Post by glitch »

As promised, I've designed, built, and written up a project for putting a modern static RAM on the OSI bus:

http://www.glitchwrks.com/2016/04/23/32k-ram-for-osi

Complete with schematics, explanations of the various blocks of the circuit, and assembly tips! This was of course built on one of the clone 495 boards I had made. The linked design is a 32K board based around the common 62256 32K x 8 SRAM, which follows JEDEC pinouts. There's a number of compatible ICs, and you can also use ROM if you like. Memory is split up into 4K segments which can be individually enabled or disabled via DIP switch, allowing you to map around existing memory without disabling it. Pretty simple to build even using point-to-point wiring.

I'll be working on adding a second SRAM and expanding the board to 64K this weekend. Another writeup will follow with details on that process. The upper 32K will be switchable like the lower 32K, to allow mapping around I/O devices and optionally enabling that 8K between 0xD000 - 0xE000 that CP/M wants on the 510 CPU board.

I designed the circuit so that a Ferroelectric RAM (FeRAM) can be swapped in, with the addition of a write protect circuit. I'll cover that in a later writeup.

Is this the sort of thing people would like to see turned into a proper board? I did the schematic in KiCad, so I'd be half the way to creating a board from the prototype. I can do a small run of them and provide either assembled/tested boards or kits.
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Parts bin Challenger 3 board set, never had a chassis in its time
dave
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Re: Building a RAM Board

Post by dave »

Nice work! I think a dedicated board with the features you describe would be very desirable, especially if it also accommodates the extra 16K from 8000-BFFF for systems without ROM BASIC. That would make it nearly a universal OSI RAM board.

Dave
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glitch
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Re: Building a RAM Board

Post by glitch »

It would include 0x8000 - 0xBFFF as well as 0xD000 - 0xEFFF for CP/M systems using the 510 CPU board, all switchable so you could disable it if you didn't want it. You could also plug in a 27256 EPROM in the second socket and put 8K BASIC in a single ROM if you don't have it on the CPU board.

Using a FeRAM in the first socket would mean you'd also have persistent memory, so if you had a BASIC program in memory, you could simply power on and jump to the warm boot address, and be right where you left off. I'm using a similar concept in my IMSAI:

http://www.glitchwrks.com/2016/03/29/fe ... ram-part-1

You can, for instance, load MITS paper tape BASIC, and when you power up the next time, it's still in memory. Just like core on a minicomputer.
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OSI Challenger 3, 510 CPU, 8" floppies, 23 MB hard disk system starting to work!
Parts bin Challenger 3 board set, never had a chassis in its time
MK14HAK
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Re: Building a RAM Board

Post by MK14HAK »

Also similar addressing available (apart from the D000 8K which is a nice addition) using BillOs board: http://osiweb.org/osiforum/viewtopic.ph ... 0&start=50
Bills board is more suited to video systems I guess. An additional 32K bank sounds interesting and making it with 40pin 600 and 48pin OSI bus capability would be great.

Nice work Glitch.
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glitch
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Re: Building a RAM Board

Post by glitch »

BillO's board is probably the more appropriate solution for C1P systems with the 40 pin DIP expansion, unless you want a 40 pin ribbon cable going to a separate daughterboard. From the looks of it, you could reprogram the GAL to give you another 32K and just stack the board on top of the lower bank board.
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OSI Challenger 3, 510 CPU, 8" floppies, 23 MB hard disk system starting to work!
Parts bin Challenger 3 board set, never had a chassis in its time
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glitch
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Re: Building a RAM Board

Post by glitch »

A box containing 114 74LS30 8-input NAND gates arrived over the weekend, so I should be able to finish building the top 32K segment once I get some down time from billable work!
Check out The Glitch Works
OSI Challenger 3, 510 CPU, 8" floppies, 23 MB hard disk system starting to work!
Parts bin Challenger 3 board set, never had a chassis in its time
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glitch
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Re: Building a RAM Board

Post by glitch »

I *finally* got time to put the second 32K bank on my prototype RAM board tonight! Required 3 more ICs including the Static RAM, and only very slight modification to the existing circuitry. I will do a full writeup with schematic changes and pictures probably tomorrow, provided my day job isn't swamped with work.

I now have 48K enabled on my system, with the upper 16K completely disabled at the moment. It's selectable on 4K boundaries just like the bottom 32K bank, which will allow for enabling 8K from 0xD000 - 0xEFFF for OSI CP/M systems. I guess my next step is to write a little RAM test routine, which I'd like to have anyway for getting the old SEMI4200 based boards I've got working. Does anyone have such a routine for 6502? If not I shouldn't have trouble with writing one.
Check out The Glitch Works
OSI Challenger 3, 510 CPU, 8" floppies, 23 MB hard disk system starting to work!
Parts bin Challenger 3 board set, never had a chassis in its time
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glitch
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Re: Building a RAM Board

Post by glitch »

And, here's the writeup:

http://www.glitchwrks.com/2016/05/17/64k-ram-for-osi

I'm probably going to turn this into a proper PC board/kit. Obviously the RAM circuit won't take up the whole board -- I was thinking of doing the rest as a buffered prototype space, with control lines for using the onboard Data Direction generator and bus buffers from the prototype area. Thoughts?
Check out The Glitch Works
OSI Challenger 3, 510 CPU, 8" floppies, 23 MB hard disk system starting to work!
Parts bin Challenger 3 board set, never had a chassis in its time
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