C1P Hardware Mod to Reduce Flicker?

[tranter]

The DOS/65 OSI manual lists an interesting hardware modification (listed below). I'm curious if anyone has tried this mod and recommends it or not.

While no hardware changes are required to run DOS/65 on C1P or SBII systems, it is strongly recommended that the following change be made.

The standard C1P and SBII CPU boards include logic to direct the video RAM address bus to the 6502 whenever the 6502 address bus is 110100xxxxxxxxxx (binary). This normally will only happen when the CPU is actually performing reads or writes to the video RAM beginning at $D000. However there are two I/O devices addressed very close to this area. The keyboard array is at $DCxx and the disk controller is at $C0xx. In both cases it is possible that at some time during the Phase 1 portion of a CPU read or write cycle, the address bus may actually be such that the video address bus is switched from the normal video address generator to the CPU. When that happens the screen will flicker. This flicker is harmless but is objectionable. The solution is simple. The 6502 really only needs to address the video RAM during the Phase 2 period of each cycle. During Phase 2 the address bus is guaranteed to be stable and hence will not cause flicker. The modification recommended is to cut the trace going to U56 Pin 2 and place a jumper between U56 Pin 2 and the Phase 2 clock signal from the 6502. Note that in some cases, if the 2114 RAMs used for the video RAM are a bit slow, this modification may not work. In that case replace the RAMs with faster devices.

Users who have modified their CPU board for larger display sizes may have already made similar or conflicting changes to the inputs to U56. Those users should adjust the modification to fit their configuration.

[tranter]

An update: I tried the mod and could not discern any difference. Maybe the difference is subtle, or depends on the revision of 600 board or speed or RAM chips.

[Scott Larson]

So the supposed problem is that addressing devices like the keyboard and the disk controller are accidentally turning on video blanking?

[Thomas]

To my knowledge, SBII revisions above B have a modified address decoder in place, using Phase 2 of the CPU. But the screen blanking was still present.

My solution for the older Rev B board was to disable the blanking IC U69 and enable phi2 on U23 Pin 4. In my case, the phase of the CPU input clock needed to be inverted as well, but it is a board with modification for larger display sizes. Not sure if this is needed for the standard display size. Now there is no visiable flicker on heavy screen access any more.
However, you may checkout my expierance with this mod for an SBII Rev B board here at the bottom of this page.
https://storage.googleapis.com/constant ... ator2.html

[IanB]

However, you may checkout my expierance with this mod for an SBII Rev B board here at the bottom of this page.
https://storage.googleapis.com/constant ... ator2.html

I came up with a mod like this for the UK101 that got published back in 1981 ( see https://osiweb.org/osiforum/viewtopic.php?f=1&t=526 ) so it's good to see there is a similar mod for the Superboard. It really should have been like that from the start as the 6502 is well suited to such synchronised memory access and this technique was used on many other 6502 based systems like the Apple II and BBC micro.

Does anyone know why it was designed like that to begin with?

I think one possible answer is that the video sub-system was based on the earlier 440B video board design which had slower 2102 RAM (650ns access time) so it couldn't support two RAM accesses per 1uS CPU cycle (one for video and one for the CPU) and thus gave priority to the CPU resulting in noise. The Superboard used 2114 RAMs and I think the slowest of those were 450ns which would be just enough to allow two RAM accesses per 1uS CPU cycle but I guess the earlier circuit wasn't redesigned to take advantage of that.

[bxdanny]

When I got my C1P in 1979 (or possibly late '78), the 2114 RAM chips were rated at 550 ns, or just slightly too slow to support two memory accesses per cycle. Within a couple of months, I realized that I had one bad RAM chip and ordered a replacement, which was rated at 450 ns.

[Thomas]

Looking into the Rev B board Semiconductor partlist, a L2114-550 was used (see TM-100 Service manual).
Rev D boards from 1980 onwards, came mostly with RAM chips from NEC, called uPd2114LC or uPD2114L-1
LC or L was standing for low cost(that's true,check the NEC databooks).
The uPD2114L-1 had max 450nsec R/W cycle time, so like you suggested, just fast enough for half of the CPU clock cycle.
On my Rev B board, all RAM chips are uPd2114LC, so doing the flicker fix was not a problem.

[Scott Larson]

If you were lucky to get a later C1P with the 450ns memory chips then you could run the 6502 at 2 MHz with a very simple mod. If I remember right, this also made the display look a little better because accessing the video memory blanked the screen twice as fast making it slightly less visible.