Modifying C8PDF to GT speed

[lowrybt1]

Is there a resource anywhere that spells out the mods, IC replacements and 65D patches necessary to upgrade a 505B and 540B to run at "GT" (4 MHZ) speed? I see from the forum that the CPU should be replaced with the 6502C NMOS and that a "GT" crystal is added to the 505B. I have a Glitchworks 64K RAM board and am hoping that it can easily deal with the sped up cycles. (Otherwise, I'd have to upgrade a bunch of chips on two 520 RAM boards if that's even an option.) Can't tell from the schematics what speed the XT/GT crystal is. Also, I'm assuming that the 2114 RAM on the 540B would need to faster than the originally installed chips.

[bxdanny]

The GT option was 3.3 MHz, not 4. The UTI manual you contributed to Mark's site confirms this, giving delay loop values of 2300 for 1 MHz, 4600 for 2 MHz, and 7590 (=3.3 * 2300) for "GT".

I never actually saw a "GT" system, but as I remember, there was something more to it than just changing the crystal to 3.3 MHz and having fast enough RAM. I think that, on a 2 MHz system, whenever the ROM / I/O area ($C000 and up) was addressed, the clock was "stretched" to be two cycles long, dropping the speed to 1 MHz for all accesses to the upper 16k of address space. With the GT systems having a clock speed that was not an integer number of Mhz, I believe there was a circuit to substitute a 1 MHz clock when that area was addressed, but I'm not at all clear on the details. Maybe it just stretched the clock to 3 cycles of the crystal, for an effective clock speed on those accesses of 1.1 MHz?

65D (starting with version 3.2, labeled "NMHz") and 65U automatically adjusted to the correct clock speed, including on "GT" machines.