restoring a second OSI

nama
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Re: restoring a second OSI

Post by nama »

Been chasing the ghost in the machine for some time now. Luckily I've got a working board that I can compare signals with. I'm at the point where I see that END BLANK is not pulsing and that seems to have a ripple effect through lots of components, and I'm now chasing down where that originates from and what it is exactly. Unfortunately I seem to be starting to go around in circles.

EDIT: I've traced the END BLANK signal to the 74157 at U3C, and then i've traced the bad signal to the 74163 at U5E and this is where I'm stuck.

I have made comparative readings from this chip on the working board and the non working board. This is what I get:

Pin Working board Non working Board

1 High low pulse--->Low
2 High low pulse--->High low pulse
3 Low-------------->Low
4 Low-------------->Low
5 Low-------------->Low
6 Low-------------->Low
7 High low pulse--->Low
8 Low-------------->Low
9 High------------->High
10 Low pulse-------->Low
11 Low-------------->No signal (possibly not connected)
12 Low-------------->No signal (possibly not connected)
13 High low pulse--->No signal
14 High low pulse--->slight pulse
15 Low-------------->No signal (possibly not connected)
16 High------------->High

Obviously there is a lot not right here, but I'm not sure where to look next. My biggest issue is I'm having difficulty knowing what exactly is an input and what's an output. I'm doing some educated guesswork.
Dave, I was wondering if you could give me some advice and help. I think I have a few possible issues here. Pin 1 is CLR and is not pulsing. Pin 10 comes from pin 15 of U5G and is low but should be pulsing. However U5G is also a 74LS163 which has CLR fed into it, so that could be causing issues with its output on pin 15. Pin 7 could also possibly be ignored for similar reasons. Pin 13 and 14 I think are outputs so probably no need to follow those lines. Do you think I should next try to I track down the reason for why CLR is not pulsing? Am I on the right track? Tired...time for sleep.

2P (1mhz 32k) - 502 + 8k + CEGMON + garbage collector fix BASIC, D&N MEM-CM9 + 24k, 540 (mono) [SOLD]
4PMF (2mhz 24k) - 505, 540, 527, D13 + 5.25" + Gotek
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dave
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Re: restoring a second OSI

Post by dave »

Hi Philip,

I do agree that from the diagram, there should be pulsed waveforms at the base and collector of that transistor, if the base is going from 0 to 1V or so. Perhaps that is a problem.

I have not worked on the 540B cards, but I think they're pretty similar to the 540A B&W cards. From my experience, it's best to start at the crystal oscillator, make sure it's working, then check the Q3 (div 6) output of the 7492 at U3B, then follow the timing division chain of 74163s along row U5, using the schematic as a guide (check pins 4,13,12,11). Then check the CS line on the 74157 to make sure it's pulsing, then go down the memory address outputs of the 74157 chips U5J,K,I (pins 9,4,12,7) to make sure each is working, with frequency halving at each pin (although if you're getting no video, you could start out just checking a couple of these pins for go/no go to isolate the problem to the timing side or the video gen side.)

Then check the address pins and CE pin on the video RAM, and the char gen, then the shift register clock.

I'm very interested in following your progress, since I have two of these boards, and would like to get both working. These boards tend to be among the most hacked in OSI systems, and as a result, sometimes they are a bit flaky.

Best regards,

Dave
dave
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Re: restoring a second OSI

Post by dave »

Looks like I was writing my last post while you were writing yours. Actually, So the problem is in the timing chain. The stuck low CLR line is a problem. That will inhibit the whole column timing counter chain. The END_BLANK signal develops as part of that chain, so it's likely a symptom but not the root. Check the NAND at location J4I (pin 11, and inputs pins 12 and 13). Then check the flipflops at U4F. If there's no activity, then check the NANDS at U5A and U6D.
nama
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Re: restoring a second OSI

Post by nama »

That was the exact direction I was going to take for testing. It's so nice to have a confirmation that I'm doing things right...for a change.
I have no training in electronics, and although I've managed to fix a lot of computers and old arcade boards, it often comes down to three things. A general understanding of where the problem lies, brute persistence, and help from many people in the community. Without the help from people on forums like this one, I'd be stuck 80% of the time and would have to rely more heavily on shotgun replacement of parts. I hate the shotgun approach as it's mostly hit and miss, and can often cause more problems that it fixes.

I will let you know how I get on with tracking down the CLR signal anomaly. I should have some time later this evening after my 3 year old goes to sleep.

Thanks again.

2P (1mhz 32k) - 502 + 8k + CEGMON + garbage collector fix BASIC, D&N MEM-CM9 + 24k, 540 (mono) [SOLD]
4PMF (2mhz 24k) - 505, 540, 527, D13 + 5.25" + Gotek
Superboard RevD - CEGMON + 610 board 24k + D13
Spares - 3 x 527, 1 x 505, Backplane
nama
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Re: restoring a second OSI

Post by nama »

Ok...had a few spare moments to look at this.

U4E - both inputs are not pulsing.
U4F - Pin 4 & 8 are connected in the schematic and are not pulsing. Pin 13 is END BLANK, and we already know this is not pulsing and I confirmed it. Pin 9 is pulsing, and Pin 10 is Pulsing too.

Checking IC's around this U4E a little reveals the following:

U4E 7400 - pin 9 high, pin 10 pulsing (this comes from pin 9 of U4F),
U5A - All inputs pulsing, and output pulsing and connects to Pin 10 U4F
U4H - Pin 3 and 4 not pulsing

So U4F may indeed be the culprit? My only remaining concern is that END BLANK not pulsing is caused by something else, and that bad END BLANK being fed into U4F is causing the issues we see, and making me assume it's bad when actually it isn't??? It's a bit of the 'chicken and the egg' thing. Is this IC bad causing CLR to be bad, and therefore causing END BLANK to be bad...END BLANK then gets fed back into this U4F possibly compounding things further. Thats what I meant previously about going round in circles...confusion!

P

2P (1mhz 32k) - 502 + 8k + CEGMON + garbage collector fix BASIC, D&N MEM-CM9 + 24k, 540 (mono) [SOLD]
4PMF (2mhz 24k) - 505, 540, 527, D13 + 5.25" + Gotek
Superboard RevD - CEGMON + 610 board 24k + D13
Spares - 3 x 527, 1 x 505, Backplane
nama
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Re: restoring a second OSI

Post by nama »

Tracking END BLANK down to its origin at 74157 U3C shows no pulsing on pin 7. It reads high.
Grounding pin 7 suddenly shows a screen full of random characters!!!! I'm close I can tell.

EDIT: The screen jumps to life when connecting pin 7 to GND. The screen however is doubled. Left side is repeating on the right, doubling the column count.

EDIT2: So checking the inputs on U3C brings me back full circle to U5E again. As far as I can tell pins 2,3,5 on U3C are pulsing. Pin 6 looks weird..says it's got a pulse, but neither high or low is registered, just a weird pulse thing. This pin connects to pin 13 output on U5E. The following are the pins readouts from U5E:

Pin 1 - low
2 - pulsing
7 - low
9 - high
10 - low
13 - Weird pulse thingy
14 - weak pulse, but it's there.

Now grounding END BLANK (screen jumps to life) changes thing quite a bit on U5E:

Pin 1 - Pulsing
2 - pulsing
7 - Pulsing
9 - high
10 - Pulsing low
13 - nothing...no pulse, no reading at all.
14 - strong pulse now

and finally the reading from the working board:

Pin 1 - Pulsing
2 - pulsing
7 - Pulsing
9 - high
10 - Pulsing low
13 - Pulsing High/low
14 - Pulsing High/Low

Well Dave, I hope you can shed some light on all these readings. I feel to be going round in circles now...I do suspect U5E though because of the wacky signal from pin 13.

2P (1mhz 32k) - 502 + 8k + CEGMON + garbage collector fix BASIC, D&N MEM-CM9 + 24k, 540 (mono) [SOLD]
4PMF (2mhz 24k) - 505, 540, 527, D13 + 5.25" + Gotek
Superboard RevD - CEGMON + 610 board 24k + D13
Spares - 3 x 527, 1 x 505, Backplane
dave
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Re: restoring a second OSI

Post by dave »

By grounding the select line of the 74157, you are selecting 32 column mode. This selects the 6 MHz dot clock (12 MHz divided by 2 by the 7492) instead of a 12 MHz dot clock, and resets the column count after 32 characters instead of 64. The three chips, U5C, G, and E are counting characters across the line. Are you getting 32 chars or 64 on the screen? From your description, it sounds like you are getting 32 characters, with a 12 mhz dot clock, which shouldn't happen together. WIthout a scope, it will be hard to tell if the counter chain is working properly, but if you have a function generator, you can remove the crystal and inject a 1 khz or lower square wave into either side, and you should be able to follow the frequency divider chain with the logic probe. If you put in a 2 Hz wave, you can also check out the 7492, to make sure it's dividing by 2. Or, you could start replacing 74163's, starting with U5E and working backwards, and the 74157, and see if the problem is fixed.

Good luck,

Dave
nama
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Re: restoring a second OSI

Post by nama »

Thanks for the reply. It's going to take me a little bit to digest what you wrote and understand it.

As for your question. I believe that the screen is displaying more that 64 characters...probably more like 80+.
See here:
http://web.me.com/lord_philip/other_com ... P_Fix.html

Looking at the screen shot in more detail it seems to start to repeat 3 times.

I do have a O-Scope. It's a little old and flaky, but it works. If you can tell me what to look for I can probe around and take photos of what I see on the scope of the screen and post them to my page.

Phil

2P (1mhz 32k) - 502 + 8k + CEGMON + garbage collector fix BASIC, D&N MEM-CM9 + 24k, 540 (mono) [SOLD]
4PMF (2mhz 24k) - 505, 540, 527, D13 + 5.25" + Gotek
Superboard RevD - CEGMON + 610 board 24k + D13
Spares - 3 x 527, 1 x 505, Backplane
dave
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Re: restoring a second OSI

Post by dave »

]The picture is very helpful. I'll include it below:
Troubleshooting: END_BLANK tied low
Troubleshooting: END_BLANK tied low
IMG_2836.jpg (140.99 KiB) Viewed 13751 times
First a disclaimer. I used to be intimately familiar with the workings of the 540A board, but that was in 1978 - 1980 or so, so I'm trying to remember, and look through the circuit, which is a bit complex; so I may be making some mistakes. I would have to break out my machine to check for sure, and am unable to to that at the moment. So, I hope I don't lead you down the wrong path, but please forgive me if I do!

Second, I somehow misread your prior post when I wrote the above reply. You were tying END_BLANK low (pin 7 of the 74157) and not the select line (pin 1). This keeps the COL_CLR line high. Normally, that line would reset the column counter and inhibit counting during the guard bands, as well as blank the video signal in the guard bands. By tying it low, you unblank the signal, and also no longer inhibit the counters after the end of the line. The *Q pin of the 7474 SR flipflop still will pulse high for 500 ns every 256 us, when the PRESET line (pin 10) pulses high, which is why the count is resetting.

From the image, and your prior description of the pin behaviors, I suspect a bad U5E. From the picture, the column counter chain seems to be at least partly working, and the U5 D,B,F,H chain also seems to be working, generating the sync, row, and column timing signals.

The narrow characters imply a 12 MHz column clock. This implies that pin 1 of U3C is high selecting the 64 column mode. The 32-char repetition could be due to resetting the count after 32 chars, which would imply a bad 74158 or due to pin 1 on U5E being stuck high or low. However, you say it's pulsing. All the pins 11,12,13,14 on U5E should be pulsing with a 50% duty cycle between high and low. If that's not the case, then there's something wrong with the chip. If you can check with your scope, you should see a 12 MHz signal on pin 1 of U5C,G,E. You should see the frequency divide by 2 to 6 MHz on pin 14 of U5C, then to 3 MHz, 1.5 MHz, 750 KHz on pins 13,12,11; 375 Khz on pin 14 of U5G, and so on; about 23.4 kHz on U5E pin 14, and 11.7 kHz on pin 13, with 50% duty cycle square waves (high and low portions should be the same duration.) Check those counter chains first, with and without the END_BLANK tied low.

Also, check pin 1 of U3C. It should be high. If it's high, then pin 4 and pin 3 should look the same on the scope (12 MHz clock), and pin 7 and pin 6 should look the same (11.7 KHz square). If it's low, then pin 4 and pin 2 should both be a 6 MHz clock, and pin 7 and pin 5 should both be a 23.4 KHz square wave. If line 1 is high, try tying it low to see what happens. If you don't mind posting the pics directly in the thread, then it would be very helpful.

Good luck!

Dave
nama
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Re: restoring a second OSI

Post by nama »

Thanks for the lengthy reply. I'm just racing out the door now, but I might have time to grab some 74163 and 74157 IC's on the way home a little later. Maybe tonight can pull out the scope and do tome poking around. Or I may just start by replacing U5G.

I did try grounding pin 1 of UC3, but in itself it doesn't do anything to the screen as it's still dead. Pin 7 (END_BLANK) needs to be grounded too. See here for results:
Screen_2.jpg
Screen_2.jpg (116.1 KiB) Viewed 13719 times
Will have more updates for you later...

Thanks
Last edited by nama on Sat Jan 07, 2012 2:23 pm, edited 1 time in total.

2P (1mhz 32k) - 502 + 8k + CEGMON + garbage collector fix BASIC, D&N MEM-CM9 + 24k, 540 (mono) [SOLD]
4PMF (2mhz 24k) - 505, 540, 527, D13 + 5.25" + Gotek
Superboard RevD - CEGMON + 610 board 24k + D13
Spares - 3 x 527, 1 x 505, Backplane
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