600D ROM support for both 24- and 48-character modes

[Steve Gray]

Well, the clock is about 4MHz, so you need 250ns or faster EPROM. There are 70ns EPROMS in DIP so you' will probably be ok. Luckily the 600 is pretty low resolution. Video timing is always tricky. It's worth trying though.

Steve

[bxdanny]

Steve Grey, ronin17,

I guess i was thinking more as a programmer and not as an engineer (which I'm not), neglecting the fact that EPROMs don't respond instantly. So I no longer think that the design I had in mind would work as is. The dot clock in 48-character mode is 8 MHz (the 4 MHz crystal frequency gets doubled), but even if the EPROM responded within the necessary 125 ns, there would still be time during which its outputs had not stabilized, which would produce odd color effects on the screen. I guess the output at the end of each cycle could be latched until the next cycle though. That could be done by adding another 74LS174 hex D flip-flop after the EPROM, right? There are 150 ns 27C16 chips available at https://www.hinkel-elektronik.com/cgi-b ... t&nr=74682, and there is probably some margin of error in the timing spec, so they may give a stable output after 125 ns. There are also 120 ns 27C256 chips available from Hinkel, but at a considerably higher price.

I worked last night at creating a schematic of sorts for what I had in mind, using ASCII characters, and this is what I came up with:

Code: Select all

U77 pin 14 or J75 pin 1       (CD0)     ->          ------
_____________________________________________ pin 8|A0  D0|pin 9       (R)       ->     DE-9F pin 3
                                                   |      |________________________________________
                                                   |      |
U77 pin 13 or J75 pin 16      (CD1)     ->         |      |
_____________________________________________ pin 7|A1  D1|pin 10      (G)       ->     DE-9F pin 4
                                                   |      |________________________________________
                                                   |      |
U77 pin 12 or J75 pin 2       (CD2)     ->         |      |
_____________________________________________ pin 6|A2  D2|pin 11      (B)       ->     DE-9F pin 5
                                                   |      |________________________________________
                                                   | 2716 |
U77 pin 11 or J75 pin 15      (CD3)     ->         |      |
_____________________________________________ pin 5|A3  D3|pin 13      (I)       ->     DE-9F pin 6
                                                   |      |________________________________________
                                                   |      |
U42 pin 9 or J75 pin 10       (VID)     ->         |      |
_____________________________________________ pin 4|A4    |pin 18->GND          GND  >- DE-9F pin 1
                                                   |      |                     ___________________
                                                   |      |pin 20->GND
U72 pin 5 or J75 pin 13     (COLOR EN)  ->         |      |
_____________________________________________ pin 3|A5    |pin 21->+5V          GND  >- DE-9F pin 2
                                                   |      |                     ___________________
                                                    ------ 

U65 pin 5                     (HS)                    ->          (HSYNC)               DE-9F pin 8
___________________________________________________________________________________________________


U65 pin 13                    (VS)                    ->          (VSYNC)               DE-9F pin 9
___________________________________________________________________________________________________

But as I said, I no longer think that this would really work.

The ROM contents would simply have been 32 repetitions of the following:

Code: Select all

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F
00 0E 00 0C 00 0A 00 06 00 09 00 0D 00 0B 00 0F
0E 00 0C 00 0A 00 06 00 09 00 0D 00 0B 00 0F 00

ronin, good luck with the cassette sound output. I'm not going to deal with that today. Others may be more likely to figure it out. If no one does in the next day or two, I'll take another look.

[Steve Gray]

Yes, you could latch the output. The 630 board does that, as does my board. Also be aware that colour monitors have different sync than monochrome. I can never remember but one (I think v-sync) needs to be inverted. So you could add an inverter, or you could have fed the sync line(s) into the eprom. You could still have issues with sync timing etc. You can get 70 ns PLCC EEPROMS (Winbond W27C0x0) which might work. I don't know.

The other option is just to copy the video section of the 630 board As you add chips to your own design you might find the 630 implementation is not that bad.

I actually had a similar idea for the C128 to change the RGBI output to various different 8-bit colour palettes (using a resistor DAC). I also thought about an EPROM at the time. Then I thought I'd use a DUAL PORT SRAM that was mapped into the CPU space so you could change the palette on the fly. Then I looked into different video RAMDAC chips.... So many ideas Of course, I never tried it, but it would have been a fun project.

One of the things I liked about the OSI machines was all the different user-designed video mods there were, and how easy it was to hack things onto them. I think adding guard-bands and having 32/64 columns would be a good mod to try on a colour 600D!

Steve

[ronin47]

Steve Grey, ronin17,

I guess i was thinking more as a programmer and not as an engineer (which I'm not), neglecting the fact that EPROMs don't respond instantly. So I no longer think that the design I had in mind would work as is. The dot clock in 48-character mode is 8 MHz (the 4 MHz crystal frequency gets doubled), but even if the EPROM responded within the necessary 125 ns, there would still be time during which its outputs had not stabilized, which would produce odd color effects on the screen. I guess the output at the end of each cycle could be latched until the next cycle though. That could be done by adding another 74LS174 hex D flip-flop after the EPROM, right? There are 150 ns 27C16 chips available at https://www.hinkel-elektronik.com/cgi-b ... t&nr=74682, and there is probably some margin of error in the timing spec, so they may give a stable output after 125 ns. There are also 120 ns 27C256 chips available from Hinkel, but at a considerably higher price.

I worked last night at creating a schematic of sorts for what I had in mind, using ASCII characters, and this is what I came up with:

Code: Select all

U77 pin 14 or J75 pin 1       (CD0)     ->          ------
_____________________________________________ pin 8|A0  D0|pin 9       (R)       ->     DE-9F pin 3
                                                   |      |________________________________________
                                                   |      |
U77 pin 13 or J75 pin 16      (CD1)     ->         |      |
_____________________________________________ pin 7|A1  D1|pin 10      (G)       ->     DE-9F pin 4
                                                   |      |________________________________________
                                                   |      |
U77 pin 12 or J75 pin 2       (CD2)     ->         |      |
_____________________________________________ pin 6|A2  D2|pin 11      (B)       ->     DE-9F pin 5
                                                   |      |________________________________________
                                                   | 2716 |
U77 pin 11 or J75 pin 15      (CD3)     ->         |      |
_____________________________________________ pin 5|A3  D3|pin 13      (I)       ->     DE-9F pin 6
                                                   |      |________________________________________
                                                   |      |
U42 pin 9 or J75 pin 10       (VID)     ->         |      |
_____________________________________________ pin 4|A4    |pin 18->GND          GND  >- DE-9F pin 1
                                                   |      |                     ___________________
                                                   |      |pin 20->GND
U72 pin 5 or J75 pin 13     (COLOR EN)  ->         |      |
_____________________________________________ pin 3|A5    |pin 21->+5V          GND  >- DE-9F pin 2
                                                   |      |                     ___________________
                                                    ------ 

U65 pin 5                     (HS)                    ->          (HSYNC)               DE-9F pin 8
___________________________________________________________________________________________________


U65 pin 13                    (VS)                    ->          (VSYNC)               DE-9F pin 9
___________________________________________________________________________________________________

But as I said, I no longer think that this would really work.

The ROM contents would simply have been 32 repetitions of the following:

Code: Select all

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F
00 0E 00 0C 00 0A 00 06 00 09 00 0D 00 0B 00 0F
0E 00 0C 00 0A 00 06 00 09 00 0D 00 0B 00 0F 00

ronin, good luck with the cassette sound output. I'm not going to deal with that today. Others may be more likely to figure it out. If no one does in the next day or two, I'll take another look.

Thanks @bxdanny, this is very interesting stuff, I'll have a dig through my EPROM collection, I have 27C16's up to 27C512's, and I'm now wondering what speeds they might be.

I'm neither an engineer nor a programmer, though I can build and repair stuff, so I'm always interested in building new things

As for the cassette, that's an odd one, I can't quite figure out the reasons why it won't work, it seems to get all the necessary clocks plus the data from the 6850, but that CLR signal has me wondering...