Designing a general purpose memory board

[Jeff]

Hi All,

I have been spending some time designing a memory board for the challenger line. I have come up with the following design and would love some input from the hardware guys on this site. My concept is to divide the memory into 8K blocks and use 28 pin sockets and 2764 Eproms and GM76C88 SRAMS. the two chips are pin compatible, so any bank can be populated with either RAM or ROM. (well, except for the first bank).
Neither chip is very expensive (under $5) and rather retro in feel, so it seems to be a good OSI fit.

UPDATE: I added an additional bank at $A000-BFFF, in case the board is used in a C4PMF, where Basic is not in ROM, or, if a patched version of Basic is preferred...(just remove the original BASIC ROMS)

Screen Shot 2015-05-04 at 7.36.32 PM.jpg (87.59 KiB) Viewed 11487 times

Thoughts, gentlemen?
/Jeff

[BillO]

Certainly looks like it would work. Very versatile too.

[MK14HAK]

I cant see 0-7FFF used for anything but RAM. Could that be one chip as per previous design?.

[Jeff]

Personally, I plan to leave the first bank empty in some cases, so I don't have to modify the system I am upgrading. And in another (my C4PMF) I plan to have it replace a 527 board, which will only be 24K (in the first 3 banks), as my 541 board has 24K on it which would collide, and since the 541 board has bitmap graphics capabilities, I don't want to replace them.

/Jeff

[BillO]

Hi Jeff,

Just had another look. You need to make sure the DD signal only goes low when the R/W line is high and a chip on the memory board is selected (read operations only). Right now it looks as though it will go low when any chip is selected for either reading or writing.

Edit: Also, it looks like the polarity of the NAND gate output is reversed. When a CS line (Yx) or DD goes low, the output of the NAND gate will go high. It looks like you'll need to bring your current output along with R/W to another two input NAND gate. That should do the trick.

The logic should be DD(out) = !(R/W & !(Y0 & Y1 & Y2 & Y3 & Y4 & Y5 & DD(in)))

[Jeff]

Hi Bill, thanks for the reply!

I have been busy breadboarding just one of the memory chips (the one at $2000 - $3FFF) and have modified the circuit as follows:

Bread.jpg (92.63 KiB) Viewed 11443 times

I put jumpers on the 600 board in place of the 8T28's and haven't used any buffers on the data bus either.....just for simplicity, and had some promising results!

Result.jpg (92.2 KiB) Viewed 11443 times

I too am experiencing odd errors, which I have no idea how to solve. Perhaps is because of noise, I don't know, nor do I know how to solve it.

My next step is to breadboard the ROM chip and see if I can keep the pin signals the same.

Baby steps
/Jeff

[dave]

Nice. You could also use just 1 SRAM and one ROM chip of sufficient size to cover the whole 64K range. Then, use one 7430 for each type of memory, using the inverted output for the /CS. You could make the 74138 outputs jumperable to enable different blocks of RAM and ROM. Or get more fine grained with 74154's. The 4K blocks would allow you to swap in the boot ROM. In that case, you'd also want to derive the Fxxx line from the Fxxx 75154 output, and the AND of A10+A11, to disable the ROM when the disk at FCxx is addressed. One 7400 would do the trick.

Another thought: you could use an FRAM instead of an EEPROM or EPROM, and allow R/W on both chips. That way, you could just write to it from the OSI itself to change the boot ROM, etc. I'd suggest just using an FRAM, which may actually work just fine, but FRAM may only last a few years if heavily used on a daily basis. Probably would last forever on a lightly used OSI, though.

Good luck,

Dave

[MK14HAK]

Sorry I didn't realise this was your design Jeff and was wondering why Bill had come up with a second !
I believe Grant got Bills design working fine. I think it caters for your ( and mine) above requirements with the bank options - does it ?

[Klyball]

Nice. You could also use just 1 SRAM and one ROM chip of sufficient size to cover the whole 64K range

The Design I am going to use has a um61512 and a 27c512 with a pld ,The credit goes to Bill on this one .
Only really use full if you can program a pld but can pick and choose in 4k blocks in any configuration usefull for my 510 when I get a copy of cp/m I will need to address D000-EFFF

I wonder if the error's your having are speed related?

I do like the retro feel though , Good job Jeff

[Jeff]

@ Grant:

Your design (or, perhaps, Bill's) sounds much more versatile than mine. It sounds like with it, you could add as much RAM or ROM to a system, essentially anywhere in the memory map as desired. Would it sit on the 48 pin bus, or would it use the 40 pin expansion? or both???
Are you going to get boards made?

Regarding my errors being related to speed, could my chips be too slow or too fast? How can it be fixed?

@ Dave: Those are fabulous ideas, but really, I am just a rookie at this and have no idea to design it in.

Here is my beauty: This is actually my first breadboarding project!

Breadboard.jpg (195.94 KiB) Viewed 11416 times

/Jeff