My 610 board build.

[ronin47]

Just by way of comparison, this is pin 8 (/CS, same as /CE) on one of the RAM IC's on the 600:

IMG20250428133058.jpg (3.78 MiB) Viewed 83 times

And this is pin 10, so R/W:

IMG20250428133120.jpg (3.66 MiB) Viewed 83 times

There is a substantial difference between the signals there and on the 610, however I still want to focus on the /CE0 and /CE1 lines on the 610 since there is nothing there, and whilst /BRW is low, it's within specs for the RAM.

My additional RAM arrived, out of 10 ICs, 2 were bad. They worked out about 95 pence an IC so I'm not too worried about an 80% good rate.

I will need to order more though, so hoping it improves, even if only to 90%

[HOWARDHB]

The diagram below shows the RAM address decode logic.
Provided that the address and data buffers are good, this part of the circuitry is where you should focus.

I recall that U4 needs to be 7417, as 74LS17 or 74HCT17 did not work.

DECODE.png (707.28 KiB) Viewed 77 times

[ronin47]

The diagram below shows the RAM address decode logic.
Provided that the address and data buffers are good, this part of the circuitry is where you should focus.

I recall that U4 needs to be 7417, as 74LS17 or 74HCT17 did not work.


DECODE.png

Thanks Howard that is a helpful diagram, as for U4, mine is a 7417 and it tests ok, but it will give me a good place to start.

Where did you find that diagram? I looked around a fair bit and could only find full schematics.

[HOWARDHB]

Attached is the 610 manual...supplied by bxdanny!

OSI 610 C1P-SBII Expander Manual.pdf

(1.44 MiB) Downloaded 6 times

[ronin47]

Ahh thanks Howard, that's brilliant

[ronin47]

The diagram below shows the RAM address decode logic.
Provided that the address and data buffers are good, this part of the circuitry is where you should focus.

I recall that U4 needs to be 7417, as 74LS17 or 74HCT17 did not work.


DECODE.png

So with the help of this diagram, I've been looking specifically at all the inputs to U18. They are all fine and have decent logic levels. What U18 doesn't have are any outputs on pins 12, 13 or 14.

Those 3 outputs are crucial to /CE generation, and based on the truth tables for the LS138, I should see output there based on the inputs to pins 1,2 & 3, which look just fine. 4,5 and 6 are correctly connected to GND & 5v.

U18 pin 12 => U17 pin 4
U18 pin 13 => U16 pin 4
U18 pin 14 => U15 pin 4

These are next on my checklist.

[HOWARDHB]

U18 bad?

Remove U15,16 and 17 and see if U18 still has it's outputs low.

[ronin47]

U18 bad?

Remove U15,16 and 17 and see if U18 still has it's outputs low.

I already tried that. The output pins, 12,13 and 14 are high, not low BTW.

I also lifted the 3 legs to see if it was something to do with the board, but I still get no output from U18 at all, and inputs look fine and within the voltage ranges specified for the LS138.

I've also tested all the LS138's in my TL866 Pro and also in the 600, they all work just fine.

I did try pulling down pin 14 and I get a signal, but It was pulled down too hard so I need to try it again with a resistor.

It's really quite odd.

EDIT: I tried a 220K pulldown like is used elsewhere on the board and I don't have the signal anymore...

[ronin47]

Howard, do you have an oscilloscope? If so could you get a screen shot of U18 12 to 15 please so I can see what I should be getting.

I'm assuming it should look similar to what is there on the CE lines for the main RAM on the 600.

Thanks.

[HOWARDHB]

I don't have one at hand.

You could write and run a simple Basic program that alternately pokes 0 and 255 to a 600D memory location, and scope the associated address decode logic circuit. Then, compare that to similarly poked 610 memory location and it's address decode circuitry?