Paddleboard and separator....again
Posted: Tue Jul 22, 2014 8:08 am
Hi everyone,
This is my second attempt at designing a new paddleboard + data separator.
I decided to make this one a little simpler and remove the motor control circuit and just focus on the basics.
I’m putting this out there so that you can all help me critique it, and hopefully check my layout. I really want to get this right the first time so I don’t have to make multiple revisions. The basic design for the separator was borrowed from the Aardvark Journal v2n6 from February 1982.
(N.B I still need to layout the PCB, and rename some of the components)
Here are the specs:
- Designed for 5.25” and 8” drives. The connections for the 5.25” were reverse engineered from the OSI A13 paddle board. The 8” drive connections were given to me by Mike as I don’t have an 8” drive setup. (Please note that the drive connectors are designed to be mounted on the solder side of the board, so the PCB layout will show them mirrored)
- JP1 sets Shugart & PC standard 5.25” drives
- JP4 & JP5 disable the data separator section for those who already have the data separator.
- TP3 is a test point for setting the timing via R1.
- TP1 & TP1 make a jumper that need to be shorted when setting the timing.
- Timing adjustment components are on the extreme right of the PCB for easy access when the board is installed in an OSI C2 or C4, and possibly others.
If you are willing to help, I’d really appreciate it if you could have a look over the layout. I'm still learning so be gentle.
Love to hear back from you all.
Phil
This is my second attempt at designing a new paddleboard + data separator.
I decided to make this one a little simpler and remove the motor control circuit and just focus on the basics.
I’m putting this out there so that you can all help me critique it, and hopefully check my layout. I really want to get this right the first time so I don’t have to make multiple revisions. The basic design for the separator was borrowed from the Aardvark Journal v2n6 from February 1982.
(N.B I still need to layout the PCB, and rename some of the components)
Here are the specs:
- Designed for 5.25” and 8” drives. The connections for the 5.25” were reverse engineered from the OSI A13 paddle board. The 8” drive connections were given to me by Mike as I don’t have an 8” drive setup. (Please note that the drive connectors are designed to be mounted on the solder side of the board, so the PCB layout will show them mirrored)
- JP1 sets Shugart & PC standard 5.25” drives
- JP4 & JP5 disable the data separator section for those who already have the data separator.
- TP3 is a test point for setting the timing via R1.
- TP1 & TP1 make a jumper that need to be shorted when setting the timing.
- Timing adjustment components are on the extreme right of the PCB for easy access when the board is installed in an OSI C2 or C4, and possibly others.
If you are willing to help, I’d really appreciate it if you could have a look over the layout. I'm still learning so be gentle.
Love to hear back from you all.
Phil
- Schematic.jpg (190.04 KiB) Viewed 7285 times
- PCB.jpg (125.04 KiB) Viewed 7285 times
